On-chip Network Optimization Strategy For Design And Simulation

With the development of DSM(Deep submicron), more and more processors are integrated in one chip, traditional buses are more likely to become a bottleneck. In order to solve this problem, NOC (Network on Chip) was proposed. NOC is a kind of flexible and scalable micro-network on chip, of which the main guild lines are network throughput, delay, resource consumption and power consumption. So, researching some methods to improve the throughput and shorten the delay of NOC and decrease the consumption of resource is meaningful for the development of NOC.In this thesis, some methods are explored and investigated for NOC design and optimization. The main works are as follows:1. We propose a novel data transfer technique for NOC. In this technique, the routing information and some control information are attached to each raw data and the attached information is transferred on dedicated wires attached to data lines. This technique reduces the length of data needed to be transferred in NOC and makes each raw data can route like a packet header which makes the arbiter design easier. The Simulation results show that this technique can improve network throughput and shorten the data average delay in network without increase resource consumption2. We propose a novel analytical model that can be used to quickly analyze and detect the potential performance bottlenecks and an efficient algorithm that optimizes the allocation of buffering resources. More precisely, given the traffic characteristic of the target application and the total budget of available buffering space, the proposed model can estimate the place of the network bottlenecks and the algorithm can assign the buffer depth for each input channel, which can improve the performance of NOC. The simulation result show: comparing with the traditional uniform buffer depth mode in NOC, this method can improve the NOC performance and can be applied with arbitrary topologies and routing algorithm.