An Adaptive Bandwidth Allocation Of The Digital Multiplex Technology

Digital multiplexing is a technique preventing signals from interference each other while transferring in the same channel. The technique combines several signals with low code rate into one signal with higher code rate, in order to improve transmission capacity and efficiency.Digital multiplexing was first used in the relay of telecommunication. Afterward, it was widely used in communication system. In recent years, communication and broadcasting system was digitalized, which resulted in new development in digital multiplexing technique. There are various techniques to implement digital multiplexing in different background. Choosing an appropriate method is very important to improve the transmission efficiency.The background of this project is that: in the system of pilot less aircraft communicating with headquarters on the ground, the aircraft needs to transfer its state information and digital image information to the headquarter. These tow signal have differences in bandwidth and transfer delay. When multiplexing these tow signals, a special technique should be taken according to their characteristics.The main work in the paper including that:According to the background of project, explore the most appropriate method to multiplex these tow different signals based on their characteristic, and try to make a compromise between transfer efficiency, resources been used and the other indexes.When a method confirmed, the whole system will be petitioned into tow function units. The over all system includes multiplexing and de-multiplexing units. While the multiplexing unit can be partitioned into code-rate adjust block and combination block, and the de-multiplexing unit can be partitioned into synchronous block, buffer block, dispatch block and code-rate adjust block. In the software environment of Quartus II, which is developed by Altera Company, every block is described using Verilog-HDL. For every block, a test vector is generated to validate the functionality of the block, which is developed under the software circumstance of Modelsim. A test vector also is generated to validate the functionality of the whole system.The hardware includes FPGA, power system, serial port and USB expand port. According to the device types, design the PCB board and test the whole hardware.In the last, the whole multiplexing system was tested. First, the programs of multiplexing unit and de-multiplexing were downloaded into tow FPGAs on different PCB boards. In order to communicate with computer, serial port program and USB port program were also developed and downloaded in PFGA. A computer sends data into the multiplexing unit through tow serial port, modeling tow signals transferring into the multiplexing unit. A cable connects the multiplexing unit and the de-multiplexing unit on tow different PCB boards, modeling a single channel. The de-multiplexing unit sends data into the other computer through serial port and USB port, modeling receiving the data. The functionality can be validated by compare the transferred data and the received data on the tow computers. Theoretically, because of the bandwidth of the combination block is 10M, the overflow of the buffer won't happen if the total code rate of the sending ends is less than 9.6875Mbp, and the maximum data delay time is less than 0.2080ms.The contribution of this paper is that: according to the background of the project, a multiplexing method is developed, which is able to adjust bandwidth dispatched to input signals automatically, and the maximum transfer delay time can also be adjusted. The system is realized on hardware and the functionality is validated by communication with computers, which proves its usefulness in practice.