Research On E1/E2 Plesiochronous Digital Multiplexing Technique Based On FPGA

Digital multiplexing is a technology for digital combination which is based on the principle of time-division multiplexing. In the digital communication network, the digital multiplexing is not only a specialized technique that keeps abreast of source coding, digital transmission and digital switching, but also the basis of technologies such as the frame justification in network synchronization, the line multiplexing in the line concentrator and the time-division splicing in digital switching. In recent years, with changes of users'demand and the development of transmission technology, the PDH (Plesiochronous Digital Hierarchy)in optical communication fields is being replaced gradually by the SDH(Synchronous Digital Hierarchy), however, PDH can be designed for different needs of different clients because of its moderate capacity, flexible configuration,low cost,and complete functions,so it has advantages in certain access situations(such as situations that have low demands for transmission capacity).This thesis makes an in-depth research on key technologies of plesiochronous digital multiplexing and demultiplexing, and designs a scheme of four-channel E1 (Europe's 30-channel pulse code modulation, or called the base group, rate is 2.048Mbps)/E2(the second group, rate is 8.448Mbps) plesiochronous digital multiplexing system based on FPGA according to the actual needs,and the scheme achieves the main functions by single-chip FPGA, this solution has an obvious advantage in integration, power consumption, cost and flexibility,etc.This thesis begins with a brief overview of development status for the digital multiplexing technology, as well as application advantages of field programmable gate array FPGA in the communications field.Based on the principle of digital multiplexing and in accordance with designed objectives, a plesiochronous digital multiplexing system program which is suitable for my subject established. Furthermore,a detailed description of circuits that constituted each module at the multiplexing-side and demultiplexing-side are given, including design ideas and implementation methods of the HDB3 encoding/decoding, positive justification/recovery,bit synchronization and frame synchronization signal extraction, E1/E2 signal multiplexing and demultiplexing.Special emphasis is placed on positive justification and recovery module,which is regarded as core part of the plesiochronous multiplexing, the module is optimized by using Gray-coding technique in FIFO, solved the problem which existed in delivery and comparison of address pointers under the exotic clocks. In integrated development environment of Quartus II,VerilogHDL language programming, the function simulation, synthesis, layout and timing simulation of each unit circuit are completed according to the top-down design principle. Finally, based on the realization of function of each section, the waveform observation and debugging of the core parts in system is carried out, and anticipated effect is achieved.