High-speed Mixed-signal Integrated Circuits For Esd Protection Technology,

With the gate oxide Thinning, the gate breakdown voltage of MOSFET reduces, which makes the electrostatic discharge (ESD) damages to integrated circuits (IC) become more and more serious. As the same time, in the high-speed and mixed-signal IC applications, there is unreconciled contradiction between the parasitic capacitance generated by high robustness ESD protection circuit and the speed of IC. This makes ESD protection circuit design has become very difficult and more important. Therefore, for the designers, the high-speed integrated circuits ESD protection technology in ultra-deep sub-micron process is a challenge. In this dissertation, the ESD protection technologies used in the high-speed and mixed-signal IC is studied, and the ESD protection circuits used in the 100Msps Pipeline ADC are designed.In this dissertation, the structure and working mechanism of GGNMOS, GGPMOS and LVTSCR are detailedly analysed. With considering the SMIC 0.18μm CMOS process and the various factor of affecting their performance parameters, the gist of choicing the ESD protection devices applying to the different ports of the high-speed and mixed-signal integrated circuits.According to the specific requirements of the different ports, the input, the output the V_DD -to- V_SS and the digital clock ESD protection circuits are designed. The input ESD protection circuit is primary-secondary scheme. The output ESD protection circuit is a GGNMOS and GGPMOS pair. The V_DD -to- V_SS and the digital clock ESD protection circuit is a GGNMOS. By raising the trigger current and holding voltage of the ESD protection devices, the latch-up of the ESD protection circuits is solved.Based on Medici, the ESD protection devices are simulated. The results show that the trigger voltage of GGNMOS is TV, which is smaller than the gate breakdown voltage of MOSFET. The second breakdown current of LVTSCR is more than 30mA/μm, therefore, in a smaller area, it can discharge the larger ESD current. The parasitic capacitance of the input ESD protection circuit is 0.25Pf, as to as that of the digital clock ESD protection circuits. The capacitance meets the requirements of the input signal and the clock signal to the load capacitance. The turn-on speed of the ESD protection devices meets the requirements of the ESD models. At last, the layout of the ESD protection devices is designed. The area of them is 20×70μm²,25×80μm² and 6×60μm², respectively.The Analysis and the Simulation results show that the ESD protection circuits designed in this paper can be used to the 100Msps Pipeline ADC.