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Analysis And Desigh Of Mixer In RF Receiver Chip

Posted on:2017-04-07Degree:MasterType:Thesis
Country:ChinaCandidate:Z F SongFull Text:PDF
GTID:2348330488974652Subject:Engineering
Abstract/Summary:PDF Full Text Request
With the rapid development of the national public undertakings intelligent industrial chain, effort and worry intelligent wireless meter reading technology gains in popularity in medium and large residential area slowly. And whether the performance of the mixer core module is good or bad of the radio receiver chip in the wireless meter will have a direct effect on the process how this intelligent changes on our lives. Therefore how to design a more practical application in engineering mixer module becomes very important. In recent years, a variety of research and design documents for the RF transceiver mixer shows that scientists generally take the linearity as the most important target of design and optimization. But there is no particularly good way when we have low requirement of linearity on some RF chip(such as the system of FSK modulation) in engineering applications. Two types of balanced mixers discussed in this paper can solve the problem efficaciously, and they can be well used in engineering applications. The main work of the study design and the main contributions are list as follows:1, Firstly I elaborate the basic theory of the mixer and the classification of RF receiver. Then the main properties of RF CMOS are described in detail, such as gain analysis, linear analysis, noise analysis and isolation analysis. In addition, the power analysis and reliability analysis which cannot be ignored in engineering applications and stability problems that may exist are discussed in detail.2, The design of a radio receiver chip which is based on engineering applications is discussed detailed. The chip specially used in wireless meter reading has a lot of advantages such as low power consumption,high gain and the gain selectable,good common mode feedback feature in multi-channel signal, and its single balanced mixer CMOS circuit has a better port isolation characteristic. As for this chip, the total power consumption is 0.33mw; gain up is 44.78 dbm, and can be switched between four values; and the system phase margin can be optimized from-57.86° to a steady state of 71.4 °.Specific summarize as followsA:The design of single-balanced mixer analyses and simulates according to simple mixer unit. Based on that, we accomplished the design that performance index meets our expectations. In core single-balanced module, the paper add design of Common mode feedback circuit,Port isolation optimization,Variable gain module. To increase conversion, gain of system the paper also adds low-frequency amplifier module.B:The paper Pre simulates many times, including: conversion simulation, linearity simulation(1db compression point, third-order intercept point IIP3), noise figure simulation(1.2k and 50?), port isolation Simulation, stability simulation(simulation system phase margin), reliability simulation(temperature, supply voltage, process corner), to do optimization to determine the final frame.C:After the design of overall layout, the paper makes post simulation with core function of the whole mixer system to set aside allowance to do with parasitic problems may occur after tap-out.D:After tape-out, we test every key performance indicators of mixer module chip and get testing analysis and results. From the results, the design of mixer has basically meet the need of application.3, To meet the need of UHF and engineering practice, the paper design a double balanced mixer CMOS circuit which the maximum gain frequency can be measured. It can be used in RF receiver chip of Wireless meter reading and diode mixer module of RF receiver chip. Specific summarized as followsA:Compared with single-balanced mixer, the double-balanced mixer circuit have batter port isolation feature. The paper use reserved optimization of common source with negative feedback to increase relative linearity. In addition, the paper also uses second-order filter structure as load and designs the measurable maximum frequency point local oscillator circuit.B:The paper also makes performance index simulation of double-balanced circuit module, including the reliability and process corner simulation to meet the need of application of RF receiver chip which is similar with the single-balanced mixer.C:At last, we design the layout of double-balanced mixer total circuit and a brief analysis.
Keywords/Search Tags:RF CMOS receiver chip, single-balanced mixer, double-balanced mixers, application engineering practice, variable gain, circuit simulation, chip testing
PDF Full Text Request
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