| This dissertation reports on the first ultralow power 900 MHz receiver realized in a 0.25 μm CMOS process. The receiver benefits from a dual-conversion zero-IF architecture to achieve a high immunity to flicker noise at zero-IF. With the help of a few high quality inductors used as load at high frequencies, the receiver, including the integrated channel select filter, dissipates 4.5 mW from a 1.5 V supply, achieving a cascade noise figure of 7.4 dB, with –25 dBm IIP3. The VCO used for LO generation, achieves a close-in phase noise of –98 dBc/Hz at an offset of 25 kHz. A test chip including the critical high frequency blocks, has been also fabricated in a moderate 0.6 μm technology, achieving a comparable performance to the 0.25 μm chip.; The dissertation also includes a theoretical model, to predict the flicker and white noise at the output of a switching mixer. The model is quite simple and intuitive, although it predicts a mixer output noise with a good accuracy compared to complicated Cadence simulations.; All the details of the design, including the choice of architecture and various circuit designs, such as LNA, mixers, and filters are discussed with a complete support from simple qualitative theories and are verified by actual measurements. |
