Turbo Decoder Algorithm Based On The Sw-log-map Algorithm And Rtl Implementation

With rapid development of wireless communication, the capability of non-error- data transmission is more and more exigent. Channel-Codec,which is the key technique of wireless communication, play a important role. This thesis aims at studying of TURBO decoder with low bit error rate, short-decode-latency, frame-length-variable characteristic, and investigates the algorithm of TURBO decoder and real-time algorithm of TURBO decoder.Firstly, the thesis discusses the basic principle of convolution code and gives description of MAP algorithm in decoding of convolution code. Then the thesis discusses basic knowledge of TURBO decoder and LOG-MAP algorithm.Next, the thesis analyzes the decode-latency of LOG-MAP and SW-LOG-MAP, and gives solution of realization of TURBO decoder on the base of SW-LOG-MAP algorithm. The thesis builds behave model in Matlab and verifies the solution of SW-LOG-MAP TURBO decoder, and discusses the bit error rate and some important parameters, which affect the performance of SW-LOG-MAP-TURBO.Finally, the thesis finishes RTL design of the SW-LOG-MAP-TURBO decoder in Verilog hardware description language. On the base of EDA function verification, the thesis discusses bit error rate and decode-latency. According to the report of synthesis, the output bandwidth of RTL design is discussed on the report of synthesis. The feasibility of RTL design is confirmed by comparison with another analogous and finished TURBO decoder.