Copper Interconnect In The Pvd Ta / Tan Barrier Layer Performance Improvements And Defect Control Study

The transistor speed is getting much faster with the scaling down, however, the time delay from parasitic capacitance and resistance of interconnects increases. Therefore, the technology of Cu interconnects associated with low-k material replace the Al interconnects. Cu has these disadvantage that it is easily to be oxidized and diffused, it need a barrier layer to protect Cu from other material like atmosphere and dielectric, and it is also required that the barrier material has the better adhesion property. The normal barrier layer technology TiN can't meet the requirements of Cu interconnect, and the TaN is used as the barrier of Cu film. Experiments shows that the barrier's resistance of via is larger than expected, and the bottom/sidewall step coverage/uniformity of via has the strong effect on interconnect resistance and reliability. Therefore, this dissertation is aimed to study the diffusion barrier process for Cu interconnects. Through the experiments, a series of experimental data is obtained, electrical test and function test. The optimized barrier deposition process is selected. The process yield and reliability are improved. The time of Degas process should be at least 180 seconds to clean entirely. Ar clean process may drift Cu to underneath barrier, so it should be short. Reactive clean has good clean efficiency, compatibility with liner opening step, compatibility with integrated (low-k) dielectric,...