System Verification And Research Of Key Algorithm Chip For LFMCW Radar Signal Processing

With the development of 5G technology and semiconductor technology and the rapid increasing radar demands of people,the research related to radar So C which take more and more high integration and complexity has becomes a hot spot.In this paper,with the support of a 24 GHz FMCW radar So C project,the hardware implementation of the radar baseband signal processing So C verification system is carried out,and the key algorithms module is implemented as a chip.This paper first introduces the principle of signal processing algorithm of LFMCW radar,uses MATLAB to simulate the algorithm of the processing scheme.In consideration of real-time requirements and resource consumption,the sawtooth waveform scheme commonly used in engineering is selected and the speed compensation method is adopted to solve the velocity distance coupling problem adopted in this design scheme.Then,based on the successful radar RF front-end chip of a 24 GHz FMCW radar project,the IF signal acquisition circuit is built,and the sampling results are verified by the simulation algorithm to verify the accuracy of the actual collected signals.On this basis,the ZYNQ chip of Xilinx company is used as the development hardware platform,and the hardware algorithm acceleration is realized in FPGA(PL terminal)by using its parallel verification characteristics.In ARM(PS terminal)for two-dimensional CFAR solution,point trace condensation solution and PC communication function.Finally,the key algorithm module FFT in signal processing is optimized and chip implemented.In the comprehensive power consumption,resource consumption,computing speed and other key performance requirements,the improved sequence structure is used to design RTL and perform function verification on FPGA.The complete ASIC backend implementation is carried out in CMOS 180 nm process.The radar signal processing system has been verified by the hardware platform,and the algorithm acceleration circuit at the PL terminal of the hardware platform can work at the main frequency of 150 MHz,and the solution time is 7.18 ms,which meets the realtime requirements of the radar signal processing system for the solution.The calculation results of the signal processing system are analyzed,and the measured distance calculation error is about 0.4m,and the velocity error is within 0.15m/s.The designed FFT processor is optimized under the traditional sequential structure,which reduces the theoretical clock cycles from 2304 to 258,and does not need extra storage resources.The actual test of FPGA shows that under the 70 MHz clock main frequency,the calculation time of a 256-point FFT is 3.7128 us,and the calculation error is less than 1.059%,which meets the requirements of FFT operation in radar signal processing.