Mpeg-4 Video Codec Dct Algorithm To Achieve

With the rapid development of multimedia communication technology, low rate and high quality video coding schemes are attracting more attention. In recent years MPEG-4 is showing great values in multimedia application because of its low-rate and object-based interchangeability. Especially simple visual profile of MPEG-4 can efficiently solve the trade-off between bitrates and video quality with relatively simple tools and algorithms, therefore, it dominates MPEG-4 applications among multimedia communication system.To meet the requirements of video application, MPEG-4 SP will be more implemented in embedded equipment. This paper attaches more importance to the embedded implementation and optimization of video coding and decoding in order to complete the development of remote video monitoring system.In this paper, after studying the core technologies and characteristics of MPEG-4 visual part, the principles of MPEG-4 SP are analysed in detail. The C language implementation for these algorithms has been done in order to evaluate the quality of reconstructed video and to validate the correctness of the program.. Then by the embedded development platform based on ARCA2 processor, hardware implementation of algorithms is established. Meanwhile, many optimizations on the two key parts----Motion Estimation and DCT are presented in order to improve the speed of video coding and decoding. The experimental results indicate that the above hardware schemes can meet many actural requirements and have some value in multimedia system. At last, ASIC implementation of DCT is studied and many optimizations or improvements measures are presented, so a solid basement is formed for IC designing of multimedia processing.The thesis is organized as following:Chapter 1 briefly introduces basic theory about video coding and decoding. Chapter 2 analyzes characteristics and main technologys of MPEG-4 visual part in detail. Chapter 3 discusses the principles of MPEG-4 SP algorithm. Chapter 4 presents an hardware implementation scheme on the embedded development platform composed of ARCA2 processor. Chapter 5 completes the optimization and implementation of ASIC on DCT. Chapter 6 gives a brief conclusion of the thesis.