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A Design And Implementation Of 16-bit Sigma-delta Audio Adc Modulator

Posted on:2007-09-01Degree:MasterType:Thesis
Country:ChinaCandidate:J FengFull Text:PDF
GTID:2208360185956120Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Σ-ΔADCs can achieve high resolution based on oversampling and noise-shaping. Comparing with conventional Nyquist converters,Σ-Δconverters greatly release the requirements for high performance of analog circuit and precisely matched components. Additionally, these converters exploit the enhanced speed, circuit density and low cost of modern VLSI technologies. Currentlly,Σ-ΔADCs have been widely used for audio A/D conversion. Furthermore, along with the rapid development of multimedia SOC chip in our country, it is exigent of developing audioΣ-ΔADCs independent. The principles ofΣ-ΔADCs are discussed firstly. Then the 16bits audioΣ-ΔADC has been designed using the Top-down design method.According with the requirements of market, the spec, the pin's function and the performance of this chip have been defined.The architecture and design methods ofΣ-Δmodulators are studied. Based on it, the bits of quantizer, oversampling-ratio and the orders of modulator have been designed. After analysing the stability of high-order single-loop modulator, a stable third-order single-loop modulator has been implemented. This novel architecture is more insensitive to the performance of analog circuit and the matching of component.The experimental modulator has been designed with fully differential switched- capacitor circuit. And the ways to optimize the circuit architecture, minimize the circuit nonidealities and improve the circuit performance are analyzed combined with the characteristics of the modulator architecture. Based on it, the switched-capacitor integrator, class A amplifier, nonoverlap clock, voltage reference, comparator, feedback DAC have been designed. In the end, the layout design is shown.This chip has been implemented in the SMIC 0.18μm CMOS process with single-poly, six-metal and MIM capacitors. Test results show that this ADC achieves the SNR of 90 dB and distortion ratio of 0.0248% for a 20KHz signal bandwidth while operating under a single 3.3V supply.This chip has been used in some multimedia SOC projects as a hard IP core.
Keywords/Search Tags:oversampling, noise-shamping, Σ-Δmodulator, ADC
PDF Full Text Request
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