Research And FPGA Implementation Of Channel Coding In DVB Systems

The most widespread application of digital image communication is the digital television broadcast system,comparing with the former analog television services,the digital television brings a new revolution on saving the frequency spectrum resources and enhancing the program quality,meanwhile,the establishment of DVB(Digital Video Broadcasting) standards has accelerated large-scale application of digital television broadcast systems.The DVB standards choose the MPEG-2 standards as the method of audio and video frequency code compression.DVB systems pack the MPEG-2 symbol streams to the form of the transport streams,and multiply these transport streams,finally transmit these streams through different mediums.In DVB transmission systems,no matter the transmission is the satellite transmission,electric cable transmission or ground transmission,in order to guarantee the picture quality and avoid the distorted phenomenon caused by the channel noise disturbance when the digital programs are in the process of transmission,we always selected the channel coding method to protect the transmission data.The channel coding is an essential and important part of the digital communication systems.The quality of channel coding design scheme has decided the success of DVB systems,this article has discussed the channel coding algorithm and FPGA realizing methods of DVB systems,the mainly works are as follows:1) Through introducing the basic concepts and characteristics of channel coding in DVB systems and deep researching on the key technologies of channel coding in DVB standards,this article analyses the main principles and the algorithms of each module.2) According to DVB channel coding characteristic,this article particularly analyses the FPGA realizing algorithms of channel coding in four key modules, including the Pseudo-random code,the RS code,the convolution-interleaving code and convolution code,then it expatiates the design scheme and function programming flow of each module and QPSK modulation. 3) In the process of the RS(204,188) encoder design,this article uses the characteristic of constant multiplier in galois field to optimize the encoder and raise the coding efficiency to a great extent.In the process of the convolution-interleaving encoder design,this article uses the RAM shifting methods to simplify the implement and reduce the FPGA resource consumption.4) The design takes the software of Altera Corporation's QuartuslI as platform, realizes the four modules and QPSK modulation by using the FPGA chip EP1C6Q240C8,uses Verilog HDL to describe the algorithms and the timing simulation to validate the feasibility of the algorithms.This article gives the methods of deburring elimination,which makes the system more stable.The final results of system simulation show that this system has worked stably and reached the design requirements.