8 - Bit Mcu Ip Core Design And Application

This paper introduces the design of an 8-bit micro controller unit IP core, SDU_M08 which adopts the instruction set of PICI6C57. The IP core based on RISC architecture only has 33 reduced instructions. Harvard architecture and two levels pipe-line structure are used, so most of the instructions only need one machine cycle to be executed and the speed is increasedThis thesis using Top-Down IC design method describes in detail the system specification, compartmentalization and design of sub modules, logic synthesis, functional simulation, gate-level simulation and so on. Different Synopsys's EDA tools are used during different design phases.During the RTL design level, the sub modules of IP core have been designed carefully. At last the functional simulation of sub modules and whole IP have been finished using Synopsys's tool VCS. Taking the reduction of power consumption and resources of the chip into prior consideration, the research and optimization of ALU are emphasized without modifying the functions. At the same time, the general registers are specially designed to improve the speed of the design.During the synthesis level, this thesis adopts the proper synthesis strategy and optimization measure to synthesize the IP core using Synopsys's Design Compiler. The netlist of synthesis has passed the gate-level simulation.The simple instructions of this SDU_M08 IP core are easy to be learned, thereby the core can be widely used in those controlling fields which require low power consumption and high ratio of performance to price. The research of this thesis would necessarily contribute to the development of more complex MCU IP core.