The Design, Based On The Fpga Serial Ata1.0a Device Ip Core

Twenty years have pasted, since the Parallel ATA protocol was designed. But nowadays, the protocol's limitation embarrasses the system's performance to improce on; On Aug₂001, the release of Serial ATA (SATA) protocol indicated the interface of the peripheral equipments, such as hard disk, was changed. Many fabless companys designed SATA IP CORE, and accelerated the popularization of the protocol, but all of them designed for IC non for FPGA, so at this time, it's significant to design an IP CORE for FPGA.This paper first introduced the SATA protocol; then the developing tools, language and chip selected for realizing this IP CORE based on FPGA; and then explained the design of the IP CORE in detail, designed a parallel structure, suit for FPGA and fulfill the protocol requirment. Besides, provided whole design block diagram, then expatiated each part of the design separately, finally, coded the design. At last, finished the whole optimization and testing.In the high speed design, this paper used the method of the pipeline for parallel design in order to improve the speed. Considering different parts have different complexity, this paper designed different pipelines for them, Adopted logiclock technology to optimize system, integrated testing modules in FPGA, it was convenient to test. Received the tested data finally, it indicated the design fulfilled the protocol's requirment.