Design And Implementation Of Jpeg2000-based Image Processing System

As an important modern technology, image processing and transition has been widely used in the following fields such as intelligence transportation, communication, military, information safety, etc. With the development of DSP tecknolodge, video codec, which is implemented in DSPs, becomes a highlight. This kind of implementation is much more flexible and more upgradeable than the video codec burned in ASICsThe content of this thesis is mainly focused on the schedule implementated on a high speed and high-resolution image processing system, which is based on PC104 bus with FPGA as its core system control part and DM642 as a GPU processor. Here we mainly research the metheds on video acquisition and video codec, as well as video data inter-communication.In this system, we use FPGA, manufatured by Altera Co. Ltd, to acquisite the image resource precisely.Also we implement high speed and complex logic design to control the whole system and PC104 interface with it. Here the captured image data is stored to SDR-SDRAM outside FPGA.Then it is compressed according to JPEG2000 compression standard .The compressed image streaming data is stored in SDR-SDRAM. Through the interface between the card and PC, the control infomation and DSP compression stage etc. can be conveniently notified.The simulation statistics indicates that the design mentioned in the paper can be conveniently and effectively appllied to the image processing card to accomplish the functions of the dataflow controls such as I2C operation,image transform parameter data transmission,SDR-SDRAM controller,PC-FPGA communication, DSP video codec etc.