Design And Optimization On High-resolution Image Processing Circuit Structure

With the development of the multimedia and consumer electronics technology,the high resolution image processing have widely been paid attention.In the field of still image processing,the resolution of image is being expanded from 8 million pixels,12 million pixels to 24 million pixels or even higher.In the area of motion picture processing,the 4K×2K and 8K×4K resolution video are promising application for the next generation video codec standard of HEVC(High Efficiency Video Coding).As a result,high performance VLSI architectures are very important for future high-resolution real-time image processing.In this thesis,the current development trends on image and video codec standard are introduced at first.Moreover,the data dependence and the structure of data flow of key algorithms in this area are analyzed.Based on our analysis results,the challenges of VLSI structure of these algorithms for future high resolution image processing are summarized.Secondly,hardware structure of inverse discrete sine transform(IDST)/ inverse discrete cosine transform(IDCT)algorithm for HEVC is proposed.variable block size IDCT/IDST is a main tool for image compression employed by HEVC,which support variable block size IDCT from 4×4 pixel to 32×32 pixel as well as IDST.In the thesis,the weakness of the previous structures are analyzed.Furthermore,the computation complexity of the HEVC IDCT/IDST are reported by using standard test sequences.Based on above analysis,a one-dimensional fully-pipelined IDCT / IDST structure is proposed for the first time.This structure is capable of increasing the hardware utilization as well as real-time processing performance.For the constant multiplication of IDCT / IDST,a new optimized structure to reduce the hardware overhead of constant multipliers is proposed.The circuit is implemented with SMIC 65 nm 1P9M technology.According to the simulation result,the design meets the real-time image processing requirements.Based on the above work,we propose a fully-pipelined 2-D IDCT/IDST structure supporting variable-sized block.In the thesis,a new memory access scheme of the transpose buffer is proposed to minimizes the architecture's stall time.For high-resolution 8K×4K image compression,we propose a high-performance variable block size IDCT/IDST architecture.The architecture can support 4 row/column IDCT/IDST calculation in parallel with higher processing performance and lower transpose memory access bandwidth.The design is implemented with SMIC 65 nm 1P9M technology and simulation result shows the design meets the real-time HEVC IDCT/IDST processing requirements.According to the image processing requirements of the high-resolution CMOS image sensor,dead pixel removal,image denoising,color conversion and enhancement,automatic white balance,gamma correction and image compression algorithms are analyzed.To optimize the quality of noise reduction and color interpolation of sensor image,a joint noise reduction and demosaicing algorithm is proposed.The SOC architecture for CMOS image processing is proposed in the thesis according to its on-chip bus bandwidth requirements.Using SMIC 65 nm 1P9M technology,the architecture is implemented and the result shows that the design meets the requirements of professional and special application digital camera.