Research On Implementation Of Digital Logic By Multi-thresholded Neuron Networks (MTNNs)

Proceeding from the mission of reducing neuron numbers in neural networks (NNs) and enhancing the information processing abilities of single neuron, as well focusing on the digital logic implementation by multi-thresholded neurons (MTNs), this dissertation makes it possible that digital logic can be implemented by a small number of neurons and the NNs realized digital logic may have high information density. Begin with analysis of binary logic implementation by single-thresholded neuron (STN), we drew a conclusion that digital logic implementation by neuron is actually a classification problem in multi-dimension space. Meanwhile, we pointed out the demerits of soluting such problem by STN. Then, the MTN and its transfer function was discussed particularly. Taking the advantage of the characteristic of nonlinear multi-zone partition in multi-dimension of MTN, an approach of employing MTN for archiving arbitrary digital logic was proposed. According to this approach, the XOR operation which needs three STNs to achieve was implemented using single MTN. Hence, the advantage of MTN over STN was shown with the facts that the NNs need fewer neurons by using MTNs than by using STNs. In addition, the Literal, AND, OR operation as three basic operations in ternary logic were separately implemented by single MTN. With these basic MTNs, arbitrary ternary function can be achieved by NNs. Due to the enhancement of the information processing abilities of single neuron, the NNs can realize the multi-valued logic (MVL). Based on the aforesaid discussion, we probed a scheme for designing the multi-thresholded neuron circuits (MTNCs). A voltage-mode synapse circuits with simple structure, high speed and high precision was designed firstly. Then, a BiCMOS technics based circuit called verdict-converting switch (VCS) was put forward as substantial components of MTNCs. Based on this, an approach was proposed for designing the circuits ofmulti-thresholded verdicting function (MTVF) at switch level. Finally, several MTNCs were designed for implementing the XOR operation and Literal, AND, OR operation in ternary logic at switch level. The result of simulation with PSPICE showed that the designed circuits had not only the correct logic function and small propagation delay but also had simple structure. What's more, when achieving the same logic function, the MTNCs decreased large amount of hardware expense compared with the STN circuits.