Design Of Low Power Digitally Controlled Oscillator For Dynamic Voltage Frequency Scaling Applications

The IoT(Internet of Things)devices introduce DVFS technology in the chip to reduce power consumption while meeting the performance requirements of chips in different workloads.The implementation of DVFS in IoT chips faces many challenges.There are several disadvantages of traditional oscillator structure such as long frequency switching time and poor output stability in DVFS applications.In order to improve the start-up and frequency switching speed and reduce the influence of PVT(Proccess,Voltage,Temperature)on the output frequency,a low-power digitally controlled oscillator based on digital frequency division and phase selection principle are proposed in this thesis.The basic principles and specific implementation methods of digitally controlled oscillators based on digital sampling and frequency synthesis scheme are proposed in this thesis.The RTC clock in the always-on area of the IoT chip is used as the reference clock,and the 32-phase high-frequency ring oscillator clock is used to sample the reference clock.The divider and frequency divisioncircuit are used to divide the sampled value.The control word generation circuit is used to convert the frequency division value obtained by the sampling circuit into a control word that meets the timing of the phase selection units.Finally,two newly designed phase selection units are used to select the phase of the ring oscillator,and select both rising and falling edge of the output clock.Three sampling methods are adopted in sampling circuit for sampling and frequency division,and automatically switches according to the operating environment,thus the time of frequency swiching can be as low as 1 reference cycle.The sampling circuit also involves clock-gating technology to reduce power consumption.The layout implementation and post-simulation of proposed design are based on TSMC40nm process,with an area overhead of 3900?m~2.The post-simulation results show that under the process corner of TT,FF and SS,when the temperature changes from-20 to 80?and the voltage changes from 0.7V to 1V,the maximum jitter of output frequency is 1.3%.Under the corner of TT-0.9V-25?,the maximum output frequency is 139MHz,the power consumption is 199.4?W,and the energy efficiency is 1.44p J/cycle.Under the corner of TT-0.7V-25?,the maximum output frequency range is 105MHz,the power consumption is113.6?W,and the energy efficiency is 1.08p J/cycle.Simulation results show that the design targets are met.