Design Of The8051Microcontroller IP Core Based On Synopsys

The chip design industry is now faced with unprecedented challenges such as increasingly complex functional requirements, shorter design cycles and higher cost. Fortunately, digital IC design based on IP reuse technology can effectively meet these series of demands. Despite the rapid development of embedded systems development technology, the low-end market is still in a great need for8-bit microcontrollers. However, Intel’s MCS-51series single-chip, the most widely used8-bit microcontroller in our country, have been difficult to satisfy the needs of some occasions due to it’s limited resources, slower pace, larger power consumption and other factors. Programmable and reusable new8051IP core hence become a new design mainstream.In this paper, the feature, instruction systems and structures of the classical8051are analyzed firstly, then needs of the overall function of the8051IP core are determined, the optimal design of the8051instruction set is given,the overall structure of the8051IP core is planned and the top-down overall design approach and the process is defined. The8051IP core consists the arithmetic logic unit module, control module, chip data memory module, timer/counter module, serial port module, interrupt handling modules and other components. Then the VHDL language is used to design and describe the8051IP core in the overall and modular form. And next software simulation is conducted for8051IP core in various levels with the ModelSim testbench and the hardware test is done based on Quartus II and FPGA. Finally, it is comprehensively optimized to satisfy the pre-set temporal and area constraints by Design Compiler in Synopsys.After software simulation and hardware test, it is showed that system of the new8051IP core is compatible with the standard MCS-51series, therofore there are no differences exists between the new and standard51MCU. What’s more, single-chip instruction storage space of the8051IP core is greater than the standard MCS-51series single-chip, the performance is better as well, and the maximum clock frequency and instruction execution efficiency is greatly improved particularly. As a result, this design is both feasible and worthwhile.