Fpga-based Blas To Accelerate System Design And Research

With the development of information society,the need of high performance computing is growing rapidly.The standard high-performance computers to calculate is the speed of the calculating speed(in particular the speed of floating-point operations),and BLAS is the most widely used math library in high performance computing area.The speed of high-performance computers is mostly decided by the CPUs,so the ratio of performance and power is very low. How to improve the effectiveness is a hot topic in the field of high-performance computing.One effective way to improve the ratio of performance and power is to use computing accelerating devices.Based on the project of National High-Performance Computer Engineering Technology Center(NHPCETC) the BLAS accelerating system is designed in this paper and this accelerating system is based on FPGA.The main work of this paper is described as followings:First,BLAS is analyzed,and the algorithm DGEMM which can be accelerated is extracted.After comparing the current multipliers and adders commonly and analyzing the advantages and disadvantages of multipliers,we designed a multiplier and an adder which is fit for this accelerating system by using FPGA resources.Rewrite the BLAS math library which is fit for this accelerating system. Finish the driver software which implements the control of the hardware and data interaction of software and hardware in kernel.Design the PCIE module,the SRAM module and the computing array module in the hardware of this system.Many of the key technology in this article have been applied,which are described as followings: In the design of math library and accelerator Ping-Pang technique is used and in the design of an accelerator pipelining is of full used.Load balance of CPU and accelerator is carried out by using task scheduling in software according to the performance of these two parts.In the BLAS accelerating system of this paper,the software can be used in most operating systems and the accelerator has many advantages such as small size,low power and so on.The test results indicate that the accelerating system can run on 300MHZ stability and the performance is 51Gflops and the ratio of performance and power is very high.