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New Power Management Circuitry, Low-power Frequency Compensation

Posted on:2006-01-16Degree:MasterType:Thesis
Country:ChinaCandidate:Q LiFull Text:PDF
GTID:2208360152498410Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
This project is supported by National 863 Item"Smart power integration technology research"(2002AA11Z1540).This smart power IC has peculiar advantages in control mode and process design. Design succsess of this power IC will become an important basis of power system on chip (PSoC). So this IC has great theory meaning and application value. When designing this novel power management IC,a dual complex pole-zero cancellation (DCPC) frequency compensation mode with gain enhanced stage (GES) for three-stage amplifier is firstly proposed in this paper; A novel control circuit of power supply management Integrated Circuit (IC) with PSM and current limit state machine is designed in this paper; Morevoer, IC layout and measure are finished. A DCPC frequency compensation mode with GES for low power & low voltage three-stage amplifier is proposed in this paper. Based on the theory of dual complex pole-zero cancellation, a frequency response similar to single-stage can be gained. Meanwhile, the effective transconductance of output stage can be increased by several times which are equal to gain of GES, and the power dissipation can be decreased when a GES is introduced. So far, the nested miller compensation (NMC) is very classical approach to realize system stability for low power & low voltage multi-stage amplifier. Under the same power dissipation, DCPC gain-bandwidth (GBW) is expected to be increased about 10 times compared to the conventional NMC approach. Moreover, this technique requires only one very small compensation capacitor even when driving a large load capacitor. The HSPICES simulation results show that a GBW of 1.23 MHz, DC gain of 111 dB, PM of 86o and power dissipation of 0.29 mW can be achieved for a load capacitor of 500 pF with a single Miller compensation capacitor of 14 pF at a ±1V supply in a standard 0.6-μm CMOS technology. A novel control circuit of power management with PSM operaton mode and current limit state machine is designed. The characteristics of energy transfer efficiency, transient response speed, load regulation and anti-perturbation have been extremely improved through pulse skip modulation and current limit state machine;...
Keywords/Search Tags:Novel Power Manager, IC, NMC, DCPC, GBW
PDF Full Text Request
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