Dvb-t Receiver System Implemented In Hardware

In March 1997, the European Telecommunication Standards Institute(ETSI) ratified a new standard for terrestrial digital television broadcasting, called DVB-T. The standard describes the various channel coding, modulation and signaling techniques, used in order to provide acceptable video quality to the home viewer. In Europe, DVB-T gained a lot of interest lately, since it offers a better utilization of the UHF frequency band. It also provides possibilities for future interactive applications such as home-shopping, banking, e-mail services and web browsing on the television set. In Sweden, Teracom AB has already started broadcasting programs using DVB-T(April 1 1999). Set top boxes, capable of receiving these programs are also available in the market from different manufacturers.In this thesis, parts of the DVB-T receiver have been implemented in hardware using Verilog. These parts are: demapper, inner deinterleaver, depuncturer and Viterbi decoder. First, models of the different elements of the DVB-Ttransmitter and receiver were developed in C language. The next step was to implement the de-mapper, inner de-interleaver, de-puncturer and Viterbi decoder in hardware.This thesis starts with a description of DVB-T. DVB-T uses OFDM (Orthogonal Frequency Division Multiplexing) multi-carrier modulation technique to transmit the MPEG-2 transport multiplex stream over the terrestrial channel. An overview of DVB-T and OFDM is given in chapter 1. Chapter 2 concentrates on the DVB-T transmitter, including a short introduction to MPEG-2 source coding and a detailed description of the channel coding. Since the DVB-T specification only describes the transmitted signal and not the receiver, a possible setup for the DVB-T receiver is given in chapter 3.One of the main objectives of this thesis is to implement some of the components from the proposed receiver design using hardware description language Verilog. The purpose of this is to provide an area power efficient implementation that can be used in a DVB-T receiver/demodulator. The hardware implementations are described in chapter 4 & 5. The design procedure and The performance of these components are described in chapter 6. is presented in chapter 6, finally following with a summary of the work and conclusions.