.4.75 Ghz Low Phase Noise Dro-pll Design And Realization

With the development of radar and wireless communications, therequest for the local oscillator is higher and higher in the system . Seekingthe oscillators with lower phase noise, more highly pure spectrum andmore highly stabilization has became the trend to develop. DRVCOs andDROs are applied abroad to frequency synthesizers and microwaveoscillators because of their excellent phase performance, spectrum purityand stability. At present in DRVCOs the type of reflect-in series and theparallel-connection reflection type are quite common, but the latter excelsthe former in the field of phase noise . This task is designing andimplementing one low phase-noise frequency source at 4.75GHz.Because of good performance of DRVCO of parallel-connectionreflection type in the field of noise, the author designed and implementedone PLL frequency source which contains DRVCO of parallel-connectionreflection type at 4.75GHz.For reducing the difficulty in designing, the author emulated andoptimized the DRO with Serenade8.71 from Ansoft Company. And thendesigned the PLL, finally debugged the hardware to get the final circuit.The paper introduces the phase-lock loop first, including itsworking theory, the design of the loop filter and noise. Then the paperanalyzes the oscillator's operational principle, classify and noise theory.In the following chapter, some kinds of dielectric resonator oscillators,esp, their operational principle, are introduced. And then the paperexpatiates the design, emulation and the implementation of hardware ofthe DRVCO in this task, and the design and debugging of the PLL. Therealizing method of the low phase noise is analyzed and the conclusion isalso given. Finally some measure are given to improve disadvantage ofthe circuit.