Font Size: a A A

X-band Low The Phase Noise Pdro Design And Realization

Posted on:2013-02-14Degree:MasterType:Thesis
Country:ChinaCandidate:X LiFull Text:PDF
GTID:2218330371460371Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
Firstly, the paper describes the oscillator and frequency source with an overview,then introduces the basic theory of the DRO(dielectric resonator oscillator) and PLL(phase locked loop), and discusses the main parameters and circuit form and so on. We had designed two kinds of DRO,one is a common-source structure DRO working at 8.75GHz, the other is a common-drain structure DRO working at about 8.8GHz. Using HFSS and ADS to simulat the cavity size of passive part and the circuit structure of active part,then test the two DRO respectively,and analysis the test results.After completing the design of DRO, a 8.8GHz PLL was designed based on ADF4106, and the design method of the parts are described in detail. Finally,the DRO, couplers, isolators, reference sources and PLL circuit are integrated in a shielding box. Then, test the whole circuit of PDRO,the test results are as follows:output power:8.1 dBm, phase noise:-94dBc/Hz@10kHz,-98dBc/Hz@100kHz,-113dBc/Hz@1MHz. Finally, analysis and summarizes the test results of PDRO,and pointed out some inadequacies of the design and give some improved suggestions.
Keywords/Search Tags:dielectric resonator, phase locked loop, phase locked dielectric resonator oscillator, phase noise
PDF Full Text Request
Related items