Dqpsk Digital Receiver Design And Implementation

This paper focus on a sub-project of the direct spread spectrum sequence digital correlator project from China Electronics Technology Group Corporation the No. 10th Research Institute(SWIET). The design objective is to implement a DQPSK digital receiver based on FPGA devices. For QPSK modulation IF signal with the 1MHz symbol rate, when the shift of carrier wave frequency within ±3KHZ, the receiver to be implemented can track and lock the carrier wave frequency and successfully complete demodulation under the lab's test environment. At last, require receiver's BER curve will approach the ideal BER curve within 3dB SNR, and require the receiver's dynamic range is not below 20dB.After introduction of the digitalization, softwarization and implementation methods for communication systems, this paper bring out the background , objective and design plan of this sub-project. And then, It discusses the transmitter's basic conceptions, and analyses the modulation methods from the mathematic viewpoint. And, based on the several optimum design principles, this paper make a detail description about the digital receiver's system design. And then, it focus on the system simulation using MATLAB and VHDL programming. After this, the paper gives out the second step simulation result from the XINLINX EDA Tools. At last, download the design into FPGA and make a system debug until getting a satisfied conclusion.One of the word, this paper gives out the digital receiver's basic theory from the viewpoint of random signal processing, gives out the details about system design, and gives out the procedure of two simulation steps and debug. This procedure can be generalized in other digital product's research.Finally,the test results showes that the design target is obtained. The receiver can correctly demodulate the IF DQPSK signal with the dynamic range (no AGC before A/D converter)between -8dBm~+16dBm.