Study On VLSI Implementation Of Symbol Synchronization For All Digital Receiver

Nowadays, with the development of communications, frequency band used by communication is becoming more and more crowded. Some communication modulation modes whose bandwidth efficiency is high are used. The feedback analog PLL demodulator in traditional digital communication system becomes difficult to be implemented. All-digital demodulation technology which has a digital open-loop structure without PLL and feedback loop is attracting more and more attention. Symbol synchronization is the key technology in all digital receiver. This dissertation is mainly concerned with the VLSI implementation of symbol synchronization. The author’s major contributions are outlined as follows:1.Based on the algorithm of digital filter and square timing in frequency domain, it is improved by using bandpass filtering on front-end Kalman filtering on back-end. The bandpass filtering reduce the variance of timing error estimate. The Kalman filtering reduce effect of noise for this process.2. A new structure bases on the Farrow structure of interpolation filter is proposed by pipelining and Parallel processing technology. Interpolation filter implements symbol synchronization by optimized sampling in all digital receiver. Its performance has a direct impact on the bit error rate of all digital receiver. It is the key to all-digital receiver that design a nicer performance of the interpolation filter. The interpolation filter is a linear time-varying filter, and the Farrow structure is very suitable for filter with the factor variable,discussion of this paper bases on the Farrow structure. The structure is improved in many ways. It can be used to improved the operational rate and reduce the complexity of filter by pipelining and Parallel processing technology3.On this basis, a new structure based on the fast FIR algorithm is proposed. It is used to reduce the complexity of the parallel Farrow structure. It can be used to improved the operational rate and reduce the complexity,too.4. An interpolation filter base on fuzzy inference is designed. Because of using changeless coefficients, the existing Farrow structure of Lagrange interpolation filter has a high bit error rate for the demodulation of high effective modulated signals. By a mass of experimentation, an interpolation filter base on fuzzy inference is designed. It can control the coefficients of filter with fractionally spaced change. Simulation and experimentation results show that the improved interpolation filter reduces bit error rate. So the good effect is gained. The Comparison of improved the structures is maked in sampling rate, hardware complexity and the of energy consumption. The impulse response, frequency response and the constellation diagram are produced by simulation. It has realize for using FPGA.