Integer multiplier and squarer architectures with overflow detection

The results of arithmetic operations are stored in fixed-sized registers. Any result that cannot be correctly represented in the result format is said to overflow and an indication of overflow is typically generated. Most general-purpose and application-specific processors support integer multiplication in hardware. Multiplication of two n-bit integers results in a 2n-bit product. Many general-purpose processors return the n least significant bits of the product and an overflow flag. Digital signal processors and multimedia processors often saturate results that overflow to the most positive or most negative representable numbers.; This dissertation presents novel methods for overflow detection in high-speed integer multiplier and squarer architectures. Compared to conventional methods for overflow detection, the proposed techniques reduce area, delay and power by only computing the n + 1 least significant product bits and detecting overflow in parallel with the multiplication or squaring. Since the techniques proposed are independent of how the multiplication is executed, they can be tailored to any multiplier design. Specific designs for array and tree multipliers with overflow detection are implemented. The proposed multiplier overflow detection circuits have similar structures for unsigned and two's complement operands. Similarities in the designs are used to develop combined multipliers, which perform either unsigned or two's complement multiplication with overflow detection, based on an input control signal.; This dissertation also presents alternative overflow detection techniques, which reduce the area of the overflow detection circuits. The proposed techniques effectively reduce the number of gates used in the overflow detection circuit, while keeping the critical delay path unchanged.; This dissertation also presents enhanced-functionality multipliers with overflow detection. These multipliers are capable of executing a double-width multiplication with overflow detection, a single-width integer multiplication with overflow detection, or a single-width fractional multiplication with result truncation. Compared to multipliers that return double-width results with overflow detection, the proposed enhanced-functionality multipliers have slightly more area, but less overall delay and less power dissipation when single-width integer and truncated fractional multiplication operations are performed. (Abstract shortened by UMI.)...