Design And Implementation Of FFT Hardware Architecture Based On FPGA

This paper takes full advantage of FPGA parallel computing, designing and implementsing high-speed configurable FPGA-based FFT processor. Which not only to achieve 64 to 2048 point FFT operation, but also can improve the operation speed and maneuverability. After considering the complexity of the operation and the difficulty of control, the mixed radix-2 and radix-4 decimation in frequency FFT algorithm is chosen to implement the FFT processor.After completing the calculation and storage of a part of the data, each level of butterfly operation can start a new level of operation without waiting for completing storage of all the data. Which can achieve a multi-stage operation, and improve the speed of the operation. In order to avoid an overflow phenomenon in butterfly operation, this paper designs a mechanism to control it.The paper analyzes the characteristics of a variety of FFT algorithm in detail through a lot of signal-flow diagrams and data tables. It also presents detailed expatiation for the processor about a variety of hardware structure, RTL-level design and method. At last, this paper presents FPGA implementation and post-layout simulation results, verifying the correctness of the whole system and every functional module.