Media Processor Design And Validation Studies

Media processor is developed rapidly in the last twenty years to meet the fast increasing demand of multimedia application. Media processor can be classified into special purpose programmable processor, general purpose programmable processor, dedicated processor and reconfigurable processor. These processors have improved the compute power to meet the media processing requirement. Reduced Instruction Set Computer (RISC) and Digital Signal Processor (DSP) have different application areas due to their different Instruction Set Architecture (ISA) and micro-architecture. RISC/DSP is a hybrid of traditional RISC and DSP processor. Merit to both characteristics of RISC and DSP, RISC/DSP is more capable for complex media processing.This paper describe a RISC/DSP processor-MediaDSP3200 serials, which isdeveloped by the Department of Information Science and Electronic Engineering in Zhejiang University. MD32 ISA is a novel architecture, which features with both RISC and DSP. Single Instruction Multi Data (SIMD) is also supported in MD32. A characterized RISC/DSP micro-architecture and unified pipeline is designed based on MD32 ISA. It is not only good at executing system tasks like RISC processor, but also expert in digital signal processing like DSP. This makes MD32 more powerful in multi-media signal processing.To verify the design of MD32 quickly, FPGA based media processor hardware/software co-simulation platform is developed. This platform includes a FPGA based hardware sub-platform and a software sub-platform running on host PC. Both the hardware and the software can be re-configured quickly to accommodate different media processor for different simulation specification. The design of co-simulation environment on MPSP is based on library. A reconfigurable IP library and a software pack with API interfaces are provided as a part of MPSP. Based on this platform, the FPGA based co-simulation processing is greatly accelerated. MD32 is simulated on this platform and the design is verified.To test the chip, DFT(design for testability) structure should be considered on the design. Test structures such as scan chain should be added to the processor. And ICE(in circuit emulator) is a indispensable component in the intergrated development environment of mdia processor. It requires an embedded debug interface. So an embedded debug interface based on JTAG is described on this paper. Based on this interface, both the structure and function test and the hardware debug such as single step,breakpoint and watch can be applied to MD32.