Based On C < Sup > * < / Sup > Core < Sup > Tm < / Sup > Risc Cpu Flash Controller Design

This thesis describes the design of an NAND flash controller based on C*Core 32-bit RISC CPU by Suzhou China-Core Technology Company and presents some typical applications with NAND Flash Memory using this controller. The purpose of the controller chip is to meet the application requirements of each NAND Flash Memory and get better performance than the currently available chips.First, we introduce all functional modules and hardware resources on the chip. It supports 32-bit data port and other control pins for NAND Flash Memory. Different from some similar chips that support only single 8-bit or 16-bit NAND Flash, we design and implement maximum four 8-bit NAND Flash Memory chips or maximum two 16-bit NAND Flash Memory chips merged into one 32-bit NAND Flash Memory chip. Controller can read and write much faster through this kinds of merge for those NAND Flash Memory with high capacity and low speed, especial for MLC and TLC.Second, we introduce the firmware structure of NAND flash controller on the chip. It consists of the FTL layer (Flash Translation Layer), the MTD layer (Memory Technology Device) and the Driver layer. In the MTD layer and driver layer, software uses auto detect mode and configurable information to package physical storage units of NAND Flash Memory which work on parallel port, interleave and some special mode, and provides a simple interface for FTL layer so that we don’t need specific code for every NAND Flash type. Software distributes key information of balance algorithm to every packaged physical units to avoid possible system crash because of losing this key information and map table can be reconstructed and repaired more easily. We design a new management information data structure, and storage method for MLC and TLC NAND Flash Memory so that some information such as lists, algorithms and ECC codes can be more effective for device balance and data reliability. At the same time, the designed firmware gives a good method for garbage collection to avoid time conflict of normal application and collection. Software program has been optimized for FAT and FAT32 file system to speed up for small file’s read and write.Finally, the thesis also describes how to manufacture a removable storage device using this controller connected with NAND Flash Memory and the performance of this device. This method divides the firmware from optimization algorithm for every NAND Flash Memory or every work mode into different space, the optimization algorithm will be written to NAND Flash Memory through mass production. Hence we can optimize every NAND Flash Memory without increasing hardware resource. Finally we set a goal to study proposals for future direction for the current design to achieve the better performance and the functionality.