Floating-point Processing Unit Structures And Algorithms Research

The work in this thesis is part of National 05' project entitled "Application Specified high performance microprocessor".There are five parts in PowerPc603e?microprocessor: Integer Execution Unit, Floating Point Unit(FPU), Instruction(Data) Cache, Bus Interface Unit and Memory Manage Unit. The instructions are executed with pipeline way. This paper studies FPU's algorithm, data-path, control-path, and implements the integration of the PowerPc603e system. This thesis mainly discusses the algorithms and the implementation of the floating point unit in the embedded PowerPc603e microrpocessor.The research work of this thesis mainly includes: Research of floating point algorithm, including addition, subtraction , multiplication , division, evolution and CORDIC(COordinate Rotation Digital Computer). Select and verify some algorithms of PowerPc603e's FPU. Design and implemention of the data-path of FPU, with emphasis in design a 64bit multiply-add unit.PowerPc603e is a complex microporcessor system. This thesis has contributed a lot to the designing of embedded microprocessor with full copyrights. The design of PowerPC603e system provided an optional method for urgent needed microprocess in aviation projects.