Fpga Implementation Of The Experimental Platform Of Broadband Rf Digital Receiver

The continuous developments of modern radar technology and the consequent more complicated electromagnetic environment have made it crucial to design wideband, digital, multifunctional software electronic reconnaissance equipment. The digital signal processing, with its superior performances over the analog processing, has drawn wide attentions in the engineering area provide an idea development mode for electronic reconnaissance system, which is different form the communication system in its wide-band processing. At present, the mismatch between the high-speed data flow of the wideband A/D converter and processing capability of the general DSP hinders the digitization of the electronic reconnaissance system most. On the other hand, the fast developments of micro-electronic technology and the wide applications of FPGA made digital circuit design more effective and afford an available method in engineering or experimentation to resolve the mismatch between high-speed A/D converters and DSP chips. This dissertation develops an emulation board for full-probability digital receiver and the implementations/verifications in FPGA. The main contributions of the dissertation are as follows.DDC (digital down-conversion) high-efficiency structure is studied to realize the variable carrier frequency band-pass signal acquisition on wideband condition. Conventional DDC down-converts digitally by digital mixing, filtering, and decimating; on condition of high-speed A/D converters, the commercial DDC is no longer applicable. Filter poly-phase decomposition method is adopted in this dissertation. The partition of the tuning channel according to the digital mixing sequence, and the digital down-conversion by means of decimating first, the low-pass filtering and mixing realize efficiently the down-conversion of the variable carrier frequency band-pass signal. And the implementations in FPGA of each composition are also completed.The rapidly frequency estimation algorism in the short data condition are implemented in FPGA to get the band position. Pipeline has been used in this dissertation to advance the performance.Some function models, like EPP port controlling, RAM groups' management, caches, and data controlling, etc., are also implemented in FPGA to support the algorism implementations.An emulation board of full-probability digital receiver is developed to realize the verification platform for the implementations of DDC and frequency estimation algorism. The EPP port is used to change data between the board and the PC. And this emulation board can be easily used to do verification for other implementations of digital processing.