Design Of Digital Multiplexing System With Single Chip FPGA

In optical communication system, the Digital Optical Transceiver is composed of send module and recive module and data interface and user-line interface and the uint of digital Multiplexing. The digital Multiplexing is used to merge signal with low rate from many channels into a high rate data, which can enlarge communication capacity and improve the rate of transfers. There are PDH and SDH in the Multiplexing system at present. The SDH will replace the PDH eventually. But the PDH has higher channel using-rate and simple equipment. It still has large fields and application values in small scope and small capacity communication network.The digital Multiplexing system is mainly composed of digital clock extracting circuit and rate justification and Multiplexing at the send end, it has Timing pulse forming circuit and De Multiplexing and rate Recovery at the receive end. The PDH Multiplexing system is realized by using many analog cicuit, which has localization in some extend:(1) The analog circuit is diffcult to integrate and is not benefit to the small equipment.(2) The analog circuit is worse in stability and antijamming.(3) The performance of the analog circuit is difficult to satisfy the need, such as the analog pll can't satisfy the requirement of noise restrain in digital clock extracting circuit.(4) The analog circuit may improve the difficult during production and debugging.In this paper, the emphases on reseaching the design and realization of digital Multiplexer in optical transceivers system. In general, this paper present the work done as below:(1) Design a low cost and medium capacity Digital Multiplexing system, which has 12 channels El interface and is realized with single chip FPGA.(2) There are HDB3 encode/decode circuit and 2Mhz digital clock extracting circuit in the chip, which predigests the design in periphery circuit.(3) In this paper we design and realize the circuit of 2M positive justification/recovery, and we solve the problem of stuffing jitter by means of utilizing digital smoothing method.(4) The design is programed in Verilog-HDL, and then we present the conclusion of computer simulation respectively.This paper's production can be used on digital optical transceivers and SoC design, and it is valueable reference for the design of multiplexing/demultiplexing system.