| This work presents the design and implementation of a reconfigurable Turbo encoder/decoder emulator built on a Xilinx FPGA development platform. It deploys efficient hardware design to improve performance and it is also reconfigurable. It allows real time selection of total frame number, the termination requirement, and the number of iterations, beside a choice of puncturing and channel reliability estimation. Other settings that require recompilation for reconfiguration include frame sizes, code rate and the number of trellis states. A simulation of 1000 one Mbit-frames requires only 6 minutes to complete versus hours or days for a software simulation on a PC.; The Turbo decoder itself has a data throughput of 2 Mbps for 8 iterations with a maximum clock frequency of 64MHz and occupies approximately 6200 configurable logic blocks of a Xilinx Virtex II FPGA. It uses the novel fixed windowing technique to reduce memory requirement, while maintaining good decoding performance. |
