Design And Implementation Of High-throughput Turbo Decoder

Turbo codes, which is almost close to the theoretical limit of Shannon decoding performance, is well known in digital communication and widely used in various of wireless communication systems, deep space communications, satellite communications and B3G mobile communication system.It is particularly critical to design high-speed Turbo decoder to meet the requirements of up to100Mbps information transmission rate on the communication system in future. In this thesis, the design of such decoder, the algorithm of turbo decoder and how to implementing it based on FPGA are investigated.Firstly, the thesis introduces the principle of turbo coding/decoding, and analysis of several commonly used decoding algorithms. Based on that, we choose Enhanced-Max-Log-MAP algorithm which provides lower complexity and better performance as our solution.In the FPGA hardware implementation, in order to get a higher decoding throughput, this thesis considers two aspects:the algorithm structure and system clock frequency. In terms of algorithm structure, the use of parallel sub-block decoding, sliding window decoding, criterion for stopping iteration and other high-speed schemes reduce decoding delay largely. A software simulation platform is also built to optimize parameters that affect the performance of the decoder. The use of "pipelining structure " and other techniques improve the system clock frequency largely also.Based on the above schemes, this thesis uses Verilog DHL to design the turbo decoding algorithm.builds hardware simulation platform It completes functional verification by Matlab and Modelsim tools, and implements the decoder in FT4000platform which based on Xilinx Virtex-6LX240T FPGA chip. Finally we analyze the decoder resource consumption and throughput. It shows that the throughput of our decoder can achieve the rate of100Mbps, in the case of Parallel8,6iteration.