Development Of 55nm CMOS Image Sensor Technology Platform

Over the past ten years, there has been a growing interest in CMOS image sensors (CIS). The CMOS image sensor has the advantage of miniaturized, low-power, and cost-effective imaging systems comparing with charge-coupled device (CCD) technology. Due to the compatibility with CMOS process, CMOS-based image sensors offer the potential opportunity to realize the powerful system on chip (SOC). This thesis studied the process technology of integrating the image sensor process into the55nm CMOS baseline process platform, the pixel related process and their influences on the image sensor performance.Firstly, the key modules of55nm CMOS process were introduced step by step, and the55nm CMOS baseline process flow was modified according to the device requirements of CMOS image pixel、the pixel circuit and its layout design. Four CIS pixel related process steps (VTMN implantation, VTHN implantation, Sensor implantation and PIN implantation) were integrated into the CMOS baseline process. The influence of salicide process to pixel performance was also studied. In order to improve the fill factor of pixel, a new contact etch process on non-silicide area has been developed to set up the55nm CMOS image sensor process platform.Then, the process tuning was carried out to study the55nm CMOS image senor full integration process, including the influence of process conditions on pixel dark current and sensitivity. Different kinds of sensitivity were achieved via different pixel processing.The creative work of this thesis includes that it proposed and developed an integration method of image sensor process based on the55nm CMOS process platform for the first time and it studied the process related effects on the pixel and image sensor performance. The result of this thesis has been applied to a good CIS production.