Research And Design Of CMOS Phase Locked Loop

Phase-locked loop is a feedback system which output signal compared with the input signal, it is a circuit which output signal can be equal with input signal in frequency and phase, is also very important module in a hybrid circuit. Phase-locked loop circuit has captured, tracking and filtering, so it is widely used in wireless communications, digital television, radio and other products. With the development of integrated circuit technology, SoC become mainstream in the design, Phase-locked loop is becoming a essential basic module in modern VLSI design, so research and design phase-locked loop is very important.By using cadence software, this subject proposed a charge pump PLL which is composed of PFD, charge pump, VCO, filter and frequency divider. All the work was accomplished based on 0.5μm CMOS technology. The PFD composed of digital gates can implement phase and frequency detection; Charge pump used switch direct control current source symmetrical structure, charge-discharge waveform is good; VCO which control circuit is voltage change into a current control section. VCO whose frequency range is 925MHz~938MHz of Telescopic OTA structure, start-up time is 6ns; Divider structure using three D flip-flop which can work well under high-speed conditions. For system debugging and simulation, control voltage stability constant is shorter than 5μs, power consumption is 1mW. Finally, the layout was accomplished, the total area is 17.94mm2.