0.35um CMOS Process Multi-frequency Output Phase-locked Loop Circuit Design

With the development of the integrated circuit technology, communication systems and microprocessors usually need different frequencies for different functional applications. The PLL circuit plays a very important role in the ICs and on-chip systems, is the most challenging areas of the analog integrated circuit design.This thesis uses a frequency synthesizer which owes a charge pump PLL with the advantages of low power, small lock difference, low jitter and wide capture range. Frequency synthesizer includes a phase detector, a charge pump, a low pass filter and a simple ring VCO to achieve low noise, high gain and high linearity of the phase-locked loop.This thesis uses0.35um CMOS process to simulate and do the layout of the circuits. Each block of the phase-locked loop circuit has been studied in details, and in accordance with a predetermined multiple frequencies outputs which designed to meet the performance of the circuit of the loop parameters to minimize the noise. The design method of loop parameters is different from the method of single frequency design, so that need to analysis the loop parameters of the different frequencies. And further more need to study its operation principle, mathematical model and elementary characteristics. The difficulty of multi-outputs design is the loop parameters, because of the different frequencies. The different divider N of PLL will affect the design of loop parameters. So use mean square values and prove it has good noise in the range of demanded frequencies by the evaluation.Another difficulty of the thesis is to design a VCO with low noise and wide frequency range. This design uses an original current source and other methods to design a reasonable Kvco and good linearity. The value of KVCO is1000MHz/V.Simulate the circuit by HSPICE, further more manufacture and test the circuit to obtain the results achieving the desired objectives. The test results shows:the output frequency can reach250MHz, the output frequency range of VCO is180M-437M, the phase noise of the center frequency240MHZ is-111dBc/Hz@lMHz and its power consumption is lower than40mW.Application:Cell phone, PMP+TV, PDA, PID, GPS, DSC and DPF.