High-speed Interconnect Signal Integrity Studies

People's demand for bandwidth has become higher and higher with the development of technology. Nowadays, Standard interfaces like XAUL, Serial ATA, PCI Express, HDMI, and FB-DIMM have emerged to provide greater throughput using serial signal rates of 2.5 to 10Gb/s. While this trend has greatly reduced the number of traces and connections within the system, it has created new challenges for bord designers when considering implementation with multiple connectors, transmission lines, vias,IC packaging, and transceiver circuits. Reliable signal transmission acrross a host board or between daughter cards on a backplane at GHz speeds compels adoption of new strategies and tools. Faced with these challenges, PCB design engineers need to try some new simulation tools to deal with these problems. Experts have predicted that the cost of logic design will greatly decrease hardware designer in the future, whereas the cost related to high speed design will account for eighty percent or more of the total cost, high speed interconnect design has become the dominant factor of system desing.This paper has made a research and simulated high speed interconnect design for the signal integrity issues. Firstly, based on the explanation of transmission line model, this paper has conducted a detailed theoretical analysis to characteristics of the differential transmission line. Secondly, it studied the basic timing for common clock and synchronous circuit architecture in the high speed interconnect system. At the same time, it also combined with a design of embedded system to make a simulating analysis on the key network part, to verify the condition on timing. Finally, the last part of this paper is about the via in the high speed design, The analysis is mainly based on the combination of 3D full wave electromagnetic and high frequency circuit simulation in frequency and time domain. We will draw some conclusion which can reduce SI issues through simulation and analysis.