High-performance Ka-band Frequency Synthesizer Design

Frequency Synthesizer is one of the core technologies in communication and electronic system. With the development of modern communication technology, frequency synthesizers are required to have wider band, higher resolution, faster frequency switching speed and lower spurious level. Microwave, due to its characteristics, is more and more applied in radar system, guidance, electronic contermeasurement, communication system and remote sensing. The purpose of this task is to develop an X~Ku band frequency synthesizer with low phase noise, fine step and low spurs level.Frequency synthesis mainly concerns about the generation of clean signals. In the first part of this thesis we introduce the main architectures used in frequency synthesis, such as direct frequency synthesis, in-direct frequency synthesis (Phase-locked loop, PLL), direct digital synthesis (DDS), and the DDS+PLL synthesis. We analyze the main advantages and disadvantages of these architectures, which mainly focus on the phase noise and spurs.Then we create the phase noise model and analyze the spurs of the main elements used in frequency synthesizer, such as PLL, mixer, frequency multiplier and frequency divider, etc. The EMI/EMC shielding is another key aspect in frequency synthesis design. So we introduce the guidelines of these shielding issues. After that we give the procedure of the system-level design of frequency synthesizer.After the system-level analysis of frequency synthesis and the requirements of the project, we propose the schematic of this low phase noise, fine frequency step, and wide-band 11.1~13.1GHz frequency synthesizer with 10MHz frequency step, based on mixer-PLL method. The main problem of this method is that by introducing the mixer in the feedback path of PLL, the relative pass-band is increased rapidly. Because of this, the ratio of the feedback-divider , N, changes in a relatively large range from 110 to 310, which (N)MAX is nearly 3 times of (N)MIN. This leads to the un-consistency of the phase noise at different frequencies at the output of the frequency synthesizer. To solve this problem, we propose a method by adjusting the parameters of the PLL dynamicly. The test results of the project prove the feasibility and validity of our method. The frequency step of the frequency synthesizer is 10 MHz. The output phase noise is -84 dBc/Hz@1kHz and -102dBc/Hz@1MHz. And the spurs level is below -65dBc.