Research On Bus Test Scheme Based On UM - BUS System

Embedded systems as a dedicated computer system has been widely used in military, aerospace, transportation and industrial control and other fields. For these applications, embedded systems are required to have high reliability and security, you can respond quickly to faults, restore the system to a usable state. Currently solution commonly used redundancy, fault tolerance and other measures to achieve, however, the reliability of communication data within the embedded redundant fault-tolerant system also needs to be improved and perfected. As the information exchange and resource sharing channels within the embedded system, the bus system requires a complete and effective testing program that can be recorded the state of bus in real time, especially when the system or equipment failure, need the data provide efficient, accurate analysis basis.This article relies on the National Natural Science Foundation of China "dynamic reconfigurable highly reliable embedded system bus (UM-BUS) study", the project proposes a high-speed bus internal within embedded computer with self-healing capabilities. In this paper, the UM-BUS system as test object, aims to study a bus testing program for complex electronic systems. In order to fully reflect the performance of UM-BUS, Based on the bus topology designed the UM-BUS integrated electronic simulation platform. The platform is designed six different terminal devices, UM-BUS nodes simulation scenarios can transmission digital, analog and video real-time data; the master node using the SPARC-V8CPU running Vx Works operating system for data acquisition and display control. As the test environment, the platform can fully demonstrate the performance of UM-BUS transmission and recovery aspects.To be able to efficiently and accurately record the working process of the bus, the program uses the bus monitor terminal (MT) connected in series to the UM-BUS system, un-filter monitor the bus communication datas. The passing M-LVDS signals can be collected into MT node; within the FPGA module processing data analysis and encapsulation protocol; in order to adapt to the needs of different test environments of UM-BUS via the on-chip RAM and the SDRAM multi-level buffer, high-speed data from the PCI-E or USB3.0can real-time transmission to PC, using software storeage data and further analysis. The program will connect MT integrated to the UM-BUS electronic simulation platform, real-time monitor communication in the simulation environment. The integrated electronic simulation platform nodes using16concurrent transmission lines, which single-channel transmission rate can reach100Mbps, incentives dynamic reconfiguration process can be tested by faults inject. By testing when there is a failure or multiple lines on the bus, UM-BUS can be reconstructed to protect the data path of the bus on the effective transmission line, the effective bandwidth of16channels can be achieved when140.3MB/S, while the remaining8active channel, the speed can be maintained74.7MB/S; MT node can obtain real-time operating data bus, and the node interface bandwidth to meet the testing requirements.