To Pn In Dtmb System And The Design And Implementation Of A 3780 - Point Fft Processor

The Time-domain Synchronous Orthogonal Frequency Division Multiplexing (TDS-OFDM) is adopted by the Chinese digital terrestrial broadcasting standard (DTMB) for its performance advantages such as fast and accurate synchronization, high spectral efficiency and high transmission data rate. In the TDS-OFDM system, Pseudo-random (PN) sequences, acting as guard interval, are inserted at the beginning of every OFDM symbol. In the DTMB receiver, the PN sequences need to be removed from the receiverd signals before the TDS-OFDM demodulation, which is implemented by the3780-point fast Fourier transform (FFT) operation. The TDS-OFDM demodulation is studied in this paper which involves two processing modules:PN removal and3780-point FFT. In the DTMB system, at least two FFT operations are required within one signal frame. Therefore, the algorithm and implementation of FFT directly affect the power, performance and the logic resources of the overall receiver implementation. The main purpose of this paper is to design a high-throughput3780-point FFT processor, which can be multiplexed by other modules of the receiver system for reducing the overall implementation cost. The research of this dissertation is unfolded as follows:Firstly, the PN removal algorithm is introduced. Then the hardware architecture and the internal logic design of PN removal module are described. The simulation results verify the module function of the hardware design.Secondly, conventional FFT algorithms are reviewed in this paper and its advantages and disadvantages are also analyzed. According to the requirement of the DTMB system, a design scheme of3780-point FFT algorithm is provided in this paper. The scheme combines a few classical algorithms, such as Cooley-Tukey, PFA and WFTA algorithm. The designed algorithm not only reduces the computational complexity of FFT, but also meets the accuracy requirements of the DTMB system.Thirdly, the hardware architecture of the FFT processor is provided, which features a high speed design. The processing speed of this module is significantly increased by using a few techniques, such as using cascade structure to the whole FFT processor, appling pingpang RAM to the the receiver block, and adopting the combination architecture of pipeline and parallel to each DFT operation units.Finally, the RTL design of the FFT module is completed by using Verilog language. The designed module is tested in the DTMB system. The test result shows that the FFT processor meets the signal to noise ratio requirement of the DTMB system. Compared with the referred3780-point FFT design, the processing speed is increased about four times, achieving the high-speed design target.