3780-point FFT IP Core Optimization Design And Implementation In DTMB System

In recent years,with the continuous development of science and technology,digital television terrestrial broadcasting has always been one of the hot spots in the neighborhood of wireless communications.In 2006,China issued the "DTMB" standard for frame structure,channel coding and modulation of digital television terrestrial broadcasting transmission systems.The DTMB system uses TDS-OFDM(Orthogonal Frequency Division Multiplexing)technology.In this system,the 3780-point FFT(Fast Fourier Transform)algorithm is an important part.This paper analyzes the DTMB system,designs a 3780-point FFT processor,and implements a CORDIC(coordinate rotation digital computation method)algorithm to implement a complex multiplier in the FFT.This article includes the following aspects:1.The CORDIC algorithm is studied.Starting from reducing the number of iterations,some of the iterative methods in the two-step scale-free factor CORDIC algorithm are combined.Finally,a variety of CORDIC algorithms are used to give implementation architecture for calculating sine and cosine values.And use Verilog language to write code,use MATLAB to analyze the data,verify its correctness,and CORDIC algorithm and complex multiplication comparison,the implementation of the architecture used to FFT algorithm used to achieve two complex multiplications.2.The 3780 point FFT algorithm is studied.The 3780 points are decomposed into 27 points and 140 points.The large point non-base-2 FFT algorithm is converted into small point FFT algorithm for calculation.The 27-point part uses the radix-3 algorithm for operations.The 140-point part is calculated using a prime factor algorithm.In the calculation,RADER algorithm and Winograd algorithm are combined,and the CORDIC algorithm is added to this part.The Chinese remainder theorem and MATLAB are used to determine the data adjustment methods at all levels.Use MATLAB to verify the correctness of the results.3.According to the implementation method determined by MATLAB,the hardware implementation architecture was established,and the code was written using Verilog language.The data analysis was performed using MATLAB to determine the feasibility of the design architecture and the calculation results met the DTMB requirements.The designed code is synthesized in the Quartus ? software.The synthesis result on the EP2C70F89C6 FPGA chip is:Total combinational functions usage is 18513;Dedicated logic registers usage is 12405;Total memory bits usage is 543592.