Fpga Technology Mapping Algorithm

FPGA technology mapping transforms a boolean network of technology-independent logic gates into one comprised of logic cells in the target FPGA architectures. The traditional mapping aims at the network coverage using LUTs, optimizing area and timing performance. Currently, the CAD algorithm is facing numerous new challenges with the advancement of FPGA design technology. This thesis focuses on FPGA technology mapping algorithm researching on area/timing performance, heterogeneous mapping and radiation-hard improvement.1. A novel technology mapping algorithm called FDMap based on structural mapping framework under LUT-based FPGA architecture is proposed. The algorithm targets complex industrial level circuits composed of sequential devices, user defined Macros, etc. An approach named FDBalance used for logic bi-decomposition produces circuits with reduced logic depth is presented. Combined with technology mapping, FDBalance can optimize the timing performance.2. Small gates, such as AND, MUX mixed with LUTs inside the CLB to increase FPGA performance demonstrates that incorporating these gates is beneficial. Because structural mapping is not convenient for heterogeneous structure, a SAT-based boolean matching algorithm FDBMap is presented to process the heterogeneous FPGA mapping. FDBMap is evaluated using the configuration with share-input LUTs and the experiment results show that it reduces logic area by 7.7% after mapping as well as improving cluster performance by 14.37% after packing.3. FPGA is vulnerable by SEU at nanometer scales for transient soft errors. Therefore, a fast fault injection and simulation platform on LUT level is proposed and it can calculate the circuit criticality against SEU when an upset occurs in LUTs or routing resources. A radiation-hard mapping method called FDRMap is proposed at the same time to improve the radiation-hard performance benefitting from feature of CLB configuration. The experimental results show that the proposed method can decrease the criticality by 32.62% with 14.06% area penalty. Compared to the partial TMR, it decreases the criticality by 12.44% and reduces the resources by 12.23%.