Research On Algorithms Of Technology Mapping For Heterogeneous FPGAs

To improve performance of modern field programmable gate arrays (FPGAs), heterogeneous architecture is adopted to reduce its power dissipation, area and latency. And electronic design automation (EDA) tools are necessary to support development based on FPGAs.This thesis studies the problem of heterogeneous FPGA technology mapping. A systematic scheme is presented to solve it. Firstly, in the design stage, an approach based on modules is used to map some design blocks to large ASIC-like sub-circuits, which is in virtue of a computer aided design (CAD) tool. Secondly, during register transfer level (RTL) synthesis, some functions, which are suitable to implement in small ASIC-like sub-circuits, are indentified. Thirdly, logic functions are mapped into lookup-tables (LUTs) with different sizes in traditional technology mapping stage. Finally, a SAT-based method is applied to solve the problem of Boolean matching for programmable logic blocks with macro-gates.Finally, the universal testing circuits are chosen to validate the proposed scheme. Results show that the latency of a key path is shorten by mapping circuits with heterogeneous LUTs. and the Boolean matching is accelerated by partitioning the inputs of programmable logic blocks into equivalence classes.