Graphic Defects In Semiconductor Lithography Process Research And Solve

Driven by the Moore's Law, the minimum feature size has been scaled down from 0.35um to 0.25um and to 90nm at present, which have been applied in mass production in China, and the 65nm and 45nm technologies is under development as well. Meanwhile, Intel is currently leading the way to push the technology to 32nm and 22nm.For the complex IC manufacturing, the UV lithography is a key process because it defines patterns with precise dimensions and locations, as well as good overlay performance. The quality of the lithography process is also crucial for subsequent etching and implantation processes.There are several important process parameters for lithography, such as critical dimension (CD), overlay and pattern defects. Among those, CD and overlay are mainly determined by the exposure parameters, including energy overlay compensation, whereas the pattern defects normally depends on some environment factors or track processing parameters.This thesis work is dedicated to study the formation and subsequent solution of some typical defects in the lithography area by optimizing the track process and regulating the environment factors. The thesis will first give an introduction of lithography and the detailed process flow, and then followed by introducing the key machines used in lithography and roadmap for lithography technique.1. Line peeling issue.In the ADI inspection, pattern peeling is the special case for small line/space size pattern. The peeling pattern is easy to be splashed to the other pattern area, which will cause some area miss-etching, while some other over-etching. To modify the spell out of HMDS (HMDS) coating parameter, and to improve the adhesion between the pattern and the substrate without impact any productivity.2. Case study and solution of the Pre-exposure Bake (PEB) delay issue for ESCAP type photo resist, which will cause T-TOP profile and further cause the pattern collapse.ESCAP photo has its obvious advantage for the photo process, (better etching resistance, less film loss and process stability), but due to its high PEB sensitivity, it is easy to be affected by the environment and suffer some more extra defects than Acetal type.By analyzing the root cause of the T-TOP and the PEB delay, we made effective correction and improvement of the environment and the process flow.3. The study and solution of the defect under litho pattern (previous layer contamination)The defect scan is only executed after the litho process, thus most previous layer related defects cannot be captured till litho process are done. And many of these defects will also impact the litho performance.For the previous layer contamination issue, improvement was made to eliminate them from the litho side.In summary, this work is dedicated to study the litho defects systematically and to make significant improvement from the aspect of track process parameter.