Low-power 65-nm Arm926ejs Designed And Implemented

With modern VLSI design matures, the IC industry has become the cornerstone of modern industrial development, and has been widely applied to the computer, communications, Internet, and manufacturing. The feature size is reduced to nano-technology when the chip speed and integration continues to increase. At the same time the increased complexity of the system design and the widespread use of mobile electronic products, the power consumption in IC design has become a problem that can not be ignored. Power directly affects the battery life of handheld electronic devices. While power consumption not only directly affect the cost of the chip and package, and the increase in power consumption will also lead to electromigration (EM) and high current density, the direct impact on the reliability of the chip. Low-power technology has become increasingly urgent. These factors have forced IC designers are increasingly concerned about the power of the assessment and optimization method.This thesis first describes in detail the development of low-power design techniques and research significance of the situation. The second it detailed analysis of the composition of power, and dynamic power and static power optimization method. Then briefly introduces the IEEE1801 standard Unified Power Format (UPF) low power design methods. Finally it begins to elaborate on the ARM_TOP chip low power design intent and the use of multi-voltage technology and power gating, and the successful completion of the ARM926EJSchip from RTL to GDSII of the whole process, and achieve the ultimate low power consumption design targets. In this thesis, it discussed in detail the physical implementation of multi-voltage technology in the process of level shifter placement and power connections and routing. Also describes in detail the physical implementation of the MTCMOS placement, control signal connections and power routing. Innovation of this thesis is:ARM926EJS based on the design requirements, using a multi-voltage technology and power gating technology. It completes the two low-power design methodology design and implementation using Synopsys UPF of 65-nanometer low-power process. In the thesis, we describe the multi-voltage technology and power gating in the physical implementation of the emergence of some important and difficult issues of depth. Especially for the level shifter placed in the power domain and the input and output power connection, MTCMOS cell placed, the connection of the power down and up control signals of MTCMOS power switch network, and MTCMOS power of connections create a new low power process as the foundation for future projects.