The Research And Design Of Key Circuit In Passive Ultra High Frequency RFID Tag Chip

Passive UHF RFID technology is a non-contact technique of automatic identification technology, the reader is according to the reflected electromagnetic signals to obtain the data from tag and thus achieve the identification of the target object. Compared with traditional identification technology, RFID electronic tags with the advantages of rewritable, big data size, small size, anti-poor environment, long life and so, has been widely used in authentication, bank cards, physical distribution, manufacturing, transportation, etc.First, the paper describes a passive UHF RFID technology system structure, communication protocol, the overall framework of the relevant theoretical basis and RFID systems. Secondly, analysis and design the key analog RF front-end circuit, including a rectifier circuit, matching circuit, backscatter modulation circuit and clock circuits. Finally, analysis and design EEPROM memory’s level shift circuit. Specific work and innovations are as follows:1. From the perspective of the energy acquired of passive tags, first, analyzing the performance of various rectifier circuits which are optional, to determine the structure of the rectifier circuit-Dickson using Native NMOS diode connected structure, and then detailed analysis and optimization of the stage of rectifier, the size of MOS transistor and the size of coupling capacitor, the conversion efficiency of rectifier can achieve as high as 40.4%, when the tag work in the most remote distance-5m; Secondly, put forward an innovative way of simulation about the input impedance of the rectifier circuit in Cadence Spectre simulation environment using port source; Finally, the analysis and design of the matching circuit is provided, so that passive tags can get the maximized energy.2. Detailed analysis of the ASK and PSK modulation circuit principle and structure of passive UHF RFID is provided, and then design a modulation circuit with a level shift circuit.3. Designed a structure using relaxation clock circuit, with no resistance, low power consumption and anti-power fluctuations, etc. The change of clock frequency is smaller than 2%, when the change of the voltage source is 10% and the change of reference current is 20%, the power consumption of clock is smaller than 2μW, the area of layout is only 70um*73μm.4. EEPROM memory circuit. The level shift circuit is reserched and designed to reduce power consumption RFID memory circuits. Based on the analysis of traditional power level shift circuit about level conversion rate, the design of a low-power six transistor level shift circuit is proposed.In this paper, the circuit is designed using SMIC 0.18μm process.