Voltage Island-based On-chip Network Optimization Design

NoC (Network on Chip) have been widely regarded and researched as an effective solution for scalable on-chip communication in SoC (System on Chip) design, where the network-based infrastructure is adopted to replace the traditional bus-based one. Energy consumption has been one of the most concerned problems in NoC design. The introduction of VFIs (voltage-frequency islands) based on GALS (globally asynchronous, locally synchronous) not only provides a strong feasibility to reduce on-chip power consumption greatly, but also solves the problems caused by distributing a single global clock signal throughout the whole chip.This thesis proposes a design methodology based on VFIs partitioning to reduce on-chip energy consumption and improve system performance. A system-level NoC platform which supports VFIs partitioning is built for simulation and verification of related issues.Chapter 1 gives the introduction of NoC. The background, key problems and the current status are introduced.Chapter 2 provides a survey of NoC technology, introduces the foundational concepts of partitioning NoC into several VFIs, and introduces the related works in VFIs-based NoC design.Chapter 3 describes the infrastructure and implementation of modules in the NoC simulation platform. Two simulation cases are carried out for demonstration.Chapter 4 proposes and validates an optimized framework which generally consists of critical-path analysis, VFI-aware partitioning, mapping and routing allocation. Simulation results show that our framework improves the on-chip performance while reduces system power consumption significantly.In chapter 5, the technique that supports shutdown of VFIs in NoC is introduced firstly, and a design framework is presented. Then a new flow-controled routing strategy named"worm"is proposed and compared with wormhole strategy. The implementation of the new strategy is described in detail, and the simulation results are given and analyzed.