Bond Analysis And Simulation Of The Voids On The Impact Of Bipolar Power Transistors

The quality of connection layer is a critical factor to reliability of power transistor and voids are mainly failure mode to it. On the basis of large quantity of experimental data, this article has researched the impact of voids on thermal resistance,SOA,thermal stress and the strength of anti-mechanical shock by employing Minitab statistical software and X-ray imaging as well as infrared thermal spectrum. In addition, a simulation study on the impact of voids on thermal resistance is done with FLOTHERM thermal analysis software. A control method is also proposed in this article while the cause of the void formation from the back metallization quality, leadframe, solder and bonding technology is analyzed.Several innovations of this article are listed as below:1. Previously engineers had different understanding about effect to transistor which came from voids. Some thought temperature is higher when voids are near center of die, but the others thought temperature is higher when voids are near edge of die. This article proved that the second viewpoint that voids near edge have more effect to transistor than near center at the same die is right.2. The smaller the voidage is, the less effect on transistor observed. At the same rate of hole, if an individual hole is bigger, thermal resistance is higher. When the rate of hole is high and voids are small, thermal resistance is lower though there are a lot of voids in the die.3. This article has researched voids how to impact current performance of transistor. SOA will reduce when voids exceed scale. As the rate of hole is higher, SOA is smaller.4. There is almost no related research about how voids impact the performance of transistor against mechanism intensity. However, this article researched from three aspects has proved that the performance of transistor against mechanism intensity is worse if the rate of hole is higher.5. This article has explained in detail the causes of void formation. This article came up with a result that big voids in center are formed by poor back metallization of chips and voids at edge are formed during assembly process.6. As for reliability, this article has exhibited the curve of failing transistors and the trend of void expansion under thermal shocks.